DE25-Standard Development Kit

Terasic's DE25-Standard - The newest generation dev kit for Altera® University Program!

 

Designed to address the applications requirements for digital logics, embedded systems, and robotics, the DE25-Standard development kit takes advantage of the Altera®  Agilex™ 5 SoC FPGA with 138K LEs to deliver 2.5x performance breakthrough and advanced feature sets such as 1GB DDR4 32-bit data bus, 64MB SDRAM, 8-channel ADC header, GPIO header, an HSMC high-speed connector, and black and light mini LCD, etc. A rich set of input and output features, such as robust switches, LEDs, seven-segment displays, and commonly-used I/O interfaces are included to meet the needs of teaching and experiments.

 

In addition, the DE25-Standard is armed with the advanced HDMI output port (1080P), a two-lane MIPI CSI / DSI connector for camera and display, and a composite RCA jack for surveillance camera. Developers can leverage the AI tensor block on the Agilex™ 5 FPGA, the MIPI CSI / DSI connector, HDMI output, and the composite RCA jack on the DE25-Standard to develop AI-related applications such as video processing and computer vision.

Terasic DE25-Standard Development Kit

Features

  • High-Performance FPGA: Powered by the Intel Agilex™ FPGA A5ED013BB32AE4S for speed and power breakthroughs.
  • Versatile Connectivity: Includes PCI Express Gen 4.0 x16, two 200G QSFP-DD connectors for network interface, and PCIe drivers.
  • Adaptable Acceleration: Offers 1GB DDR4 with 32-bit data bus (no ECC), shared with FPGA for efficient data processing.
  • Intel OpenCL™ Support: Fully compatible with Intel OpenCL™ BSP and Intel oneAPI Toolkits for optimal Computer Vision and Deep Learning solutions.
  • Comprehensive System Monitoring: Equipped with temperature sensors, power monitors, auto fan control, and shutdown control for efficient operation.

Block Diagram

Terasic DE-25 Block Diagram