Altera® Cyclone® 10 GX FPGA

The Altera Cyclone 10 GX FPGA uses a column I/O structure with 12.5 Gbps transceivers located on the left-hand side of the die. The GPIOs are arranged in vertical columns with 48 I/Os per bank, each with its own high-efficiency memory controller and I/O phase-locked loop (PLL). Additionally, each GPIO bank supports LVDS pairs with a differential input and output buffers for the Altera Cyclone 10 GX FPGA, which can be configured for each pair at speeds of up to 1.4 Gbps.