SLVS-EC 3.0 RX IP
The latest generation CMOS image sensor interface
SLVS-EC v3.0 Rx IP is an interface IP core that runs on Altera® FPGAs. By using this IP core, you can quickly and easily create products that support the latest SLVS-EC standard v3.0. An evaluation kit is also provided for early adoption.
- Realizing receive function from SLVS-EC interface using Altera® FPGA
- Supports the latest SLVS-EC Specification Version 3.0
- Powerful De-Skew function that allows you to design boards without having to worry about skew between lanes.
- "Evaluation kit" (described below) is available for speedy evaluation of actual devices
SLVS-EC Standard Overview
- SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock) is an interface standard for high-resolution, high-speed image sensors developed by Sony Semiconductor Solutions Corporation.
- The SLVS-EC standard is being standardized by the Japan Industrial Imaging Association (JIIA).
Features
- Supports SLVS-EC Specification Version 1.2/2.0 and the latest 3.0
- Realizes various functions defined in the SLVS-EC Link layer
- 32 or 64 pixel selectable output interface
- Supports 8, 10, 12, 14, 16 bits per pixel - By utilizing the features of GCC (Gigabit Channel Coding) added in the latest SLVS-EC Version 3.0, transmission with less overhead compared to conventional ANSI 8b10b is achieved.
- Supports error correction function using ECC (Error Correction Code)
- Supports Byte to Pixel conversion in 1, 2, 4, 6, and 8 lane configurations
- Includes header parsing and payload error detection
- Unnecessary functions can be removed using compile options.
Specifications
| Features | SLVS-EC 3.0 Specifications | Macnica IP Core SUpported Specs | |
|---|---|---|---|
| Number of Lanes | 1, 2, 4, 6, 8 | YES *1 | |
| Baud Rate | Grade 1 (1.152 to 1.25 Gbps) | x | YES |
| Grade 2 (2.304 to 2.5 Gbps) | x | YES | |
| Grade 3 (4.608 to 5.0 Gbps) | x | YES | |
| Grade 4 (9.216 to 10.0 Gbps) | x | YES | |
| Bit per Second | 8, 10, 12, 14, 16 | YES | |
| Packet Footer CRC | x | YES | |
| ECC | Option 1, 2 | Option 1, 2 *2 | |
| Coding | ANSI 8b/10b / GCC | ANSI 8b/10b / GCC | |
*1: Fixed by compiler option
*2: Limited support for Option 2
Supported Devices (Altera FPGAs)
- Arria® 10 FPGA *Released at the end of June 2024
- Agilex™ 7 FPGA *Released at the end of June 2024
- Agilex™ 5 FPGA *Scheduled for release in 2024
*Please contact us for details on our SLVS-EC v3.0 Rx IP for Agilex™ 5 FPGA.
Evaluation Kit - Luminous Platform
Orders are scheduled to begin in the summer of 2024. Please contact us for details on availability etc.
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